Kioxia Corporation and Sandisk Corporation have introduced groundbreaking advancements in 3D flash memory technology, achieving a remarkable 4.8Gb/s NAND interface speed, enhanced power efficiency, and improved density.
Revolutionary Memory Technology
This innovative 3D flash memory was unveiled at the ISSCC 2025 event. It features the companies’ unique CBA (CMOS directly Bonded to Array) technology (1), which adheres to the latest interface standard, Toggle DDR6.0 for NAND flash memory. Additionally, it utilizes the SCA (Separate Command Address) protocol (2) for command address inputs and employs PI-LTT (Power Isolated Low-Tapped Termination) technology (3) to significantly reduce power consumption.
Performance Enhancements
The new generation of 3D flash memory is anticipated to deliver a 33% increase in NAND interface speed compared to the 8th Generation 3D flash memory currently being mass-produced, reaching 4.8Gb/s. With this technology, power efficiency for data input/output is also enhanced, leading to a 10% reduction in power consumption during input and 34% during output. The design improvements include an increase in memory layers to 332, optimizing floor plans to achieve a 59% boost in bit density.
Insights from Industry Leaders
Kioxia’s CTO, Hideshi Miyajima, stated, “With the proliferation of AI technologies, the volume of data produced is expected to rise significantly, necessitating improved power efficiency in modern data centers. We believe this new technology will support larger capacities, enhanced speeds, and reduced power consumption in future SSDs and aid in the development of AI.”
Alper Ilkbahar, Senior Vice President of global strategy and technology at Sandisk, remarked, “As AI progresses, the demand for diversified memory options is increasing. Our CBA technology innovation will allow us to launch products that best balance capacity, speed, performance, and cost-effectiveness for our customers across all market segments.”
Future Developments
Kioxia and Sandisk also revealed plans for their upcoming 9th Gen 3D flash memory. Utilizing their CBA technology, they aim to merge new CMOS technology with existing memory cell technology, resulting in capital-efficient, high-performance, low-power products. Both companies are dedicated to advancing cutting-edge flash memory solutions tailored to customer requirements, contributing to the growth of the digital landscape.
(1) This technology enables separate manufacturing of each CMOS wafer and cell array wafer under optimized conditions, which are then bonded together.
(2) This approach separates the buses for Command/Address inputs and data transfer, allowing for parallel usage and reducing data input/output time.
(3) This method utilizes power sources for both standard and lower voltages within NAND interfaces to decrease power consumption during data input/output.
